Industrial Inverters? The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. HCPL; per reel. HCPLJ; per reel.. Option data sheets available. Contact Agilent sales representative or authorized distributor.

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The LED is optically coupled to an integrated circuit with a power output stage. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. Wide operating VCC range: 15 to 30? Industrial temperature range:? Industrial inverters?? Switch mode power supplies A 0. F bypass capacitor must be connected between pins 5 and 8. Contact Avago sales representative or authorized distributor. To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Lot ID 1. Conditions Measured from input terminals to output terminals, shortest distance through air.

L 7. Minimum Internal 0. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. For creep? There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creep?

Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. Maintenance of the safety data shall be ensured by means of protective circuits.

Test Conditions Fig. Symbol Min. Test Conditions?? See Applications section for additional details on limiting IOH peak. The maximum LED junction tem-pera? In this test V OH is measured with a dc load current. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

Pins 1 and 4 need to be connected to LED common. VOH vs. HCPL fig 1 Figure 2. IOH vs. HCPL fig 2 Figure 3. HCPL fig 3 0. VOL vs. HCPL fig 4-new Figure 5. IOL vs. HCPL fig 5-new Figure 6. HCPL fig 6 3. ICC vs. Figure 8. IFLH vs. Propagation delay vs. HCPL fig 10 Figure HCPL fig 11 Figure Figure TransferHCPL characteristics. Input current vs. IOH test circuit.

IOL Test circuit. VOH Test circuit. HCPL fig 18 1 8 0. VOL Test circuit. IFLH Test circuit. UVLO test circuit. CMR test circuit and waveforms. Recommended LED drive and application circuit. The VOL value of 2? V in the pre? This results in lower peak currents more margin than predicted by this analysis.

When negative gate drive is not used VEE in the previous equation is equal to zero volts. The HCPL total power dissipa? J 20 kHz?? The thermal resistance values given in this model can be used to calculate the tempera? As shown by the model, all heat generated flows through qCA which raises the case temperature TC accordingly.

The value of qCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of qCA? The absolute maximum power dissipation derating specifica? Thermal model. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler.

For example, the recommended application circuit Figure 25 , can achieve 25? Techniques to keep the LED in the proper state are discussed in the next two sections. Optocoupler input to output capacitance model for unshielded optocouplers. Optocoupler input to output capacitance model for shielded optocouplers. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient.

A minimum LED cur? Figure 33 is an alternative drive circuit which, like the recommended applica-tion circuit Figure 25 , does achieve ultra high CMR performance by shunting the LED in the off state. VF OFF during common mode transients. Equivalent circuit for figure 25 during common mode transient. HCPL fig 31 Figure Not recommended open collector drive circuit.

Under voltage lock out. When the HCPL output is in the high state and the supply voltage drops below the? Dead time is the time period during which both the high and low side power transistors Q1 and Q2 in Figure 25 are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails.

Minimum LED skew for zero dead time. Waveforms for dead time. The amount of delay necessary to achieve this condi? The maximum dead time is equivalent to the difference between the maximum and minimum propa? The maximum dead time for the HCPL is ? Note that the propagation delays used to calculate PDD and dead time are taken at equal tempera? Data subject to change. All rights reserved.





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