TLV2544 PDF

A This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters SAR ADCs. The input structure of the ADC is examined along with the driving circuit. These devices have three digital inputs and a 3-state output [chip select CS , serial input-output clock SCLK , serial data input SDI , and serial data output SDO ] that provide a direct 4-wire interface to the serial port of most popular host microprocessors SPI interface. The sample-and-hold function is automatically started after the fourth SCLK edge normal sampling or can be controlled by a special pin, CSTART, to extend the sampling period extended sampling. The conversion clock OSC and reference are built-in.

Author:Kagalkis Kegrel
Country:El Salvador
Language:English (Spanish)
Genre:Career
Published (Last):24 May 2007
Pages:188
PDF File Size:8.56 Mb
ePub File Size:17.92 Mb
ISBN:449-2-72132-483-2
Downloads:28678
Price:Free* [*Free Regsitration Required]
Uploader:Araran



A This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters SAR ADCs. The input structure of the ADC is examined along with the driving circuit. These devices have three digital inputs and a 3-state output [chip select CS , serial input-output clock SCLK , serial data input SDI , and serial data output SDO ] that provide a direct 4-wire interface to the serial port of most popular host microprocessors SPI interface.

The sample-and-hold function is automatically started after the fourth SCLK edge normal sampling or can be controlled by a special pin, CSTART, to extend the sampling period extended sampling. The conversion clock OSC and reference are built-in. The converter can use the external SCLK as the source of the conversion clock to achieve higher up 2. Two different internal reference voltages are available. An optional external reference can also be used to achieve maximum flexibility.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On all other products, production processing does not necessarily include testing of all parameters. TLV I Analog signal inputs. The analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal 1 k. SDI is disabled within a setup time after the 4-bit counter counts to 16 clock edges or a low-to-high transition of CS whichever happens first.

This terminal controls the start of sampling of the analog input from a selected multiplex channel. Tie this terminal to VCC if not used. End of conversion or interrupt to host processor.

EOC is used in conversion mode 00 only. The falling edge of INT indicates data are ready for output. DSP frame sync input. Indication of the start of a serial data frame in or out of the device. A high-to-low transition on the FS input resets the internal 4-bit counter and enables SDI within a maximum setup time. See the date code information section, item 1. Ground return for the internal circuitry.

Unless otherwise noted, all voltage measurements are with respect to GND. Both analog and reference circuits are powered down when this pin is at logic zero. Input serial clock.

This terminal receives the serial SCLK from the host processor. When programmed, it may also be used as the source of the conversion clock. Serial data input. The input data is presented with the MSB D15 first.

The configure write commands require an additional 12 bits of data.

I TEST PSICOATTITUDINALI PER TUTTI I CONCORSI PDF

TLV2544ID PDF Datasheet浏览和下载

These devices have three digital inputs and a 3-state output [chip select CS , serial input-output clock SCLK , serial data input SDI , and serial data output SDO ] that provide a direct 4-wire interface to the serial port of most popular host microprocessors SPI interface. The sample-and-hold function is automatically started after the fourth SCLK edge normal sampling or can be controlled by a special pin, CSTART, to extend the sampling period extended sampling. The conversion clock OSC and reference are built-in. The converter can use the external SCLK as the source of the conversion clock to achieve higher up to 2. Two different internal reference voltages are available. An optional external reference can also be used to achieve maximum flexibility. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LEY SB1070 DE ARIZONA PDF

Interfacing the TLV2544 A/D to C5509 DSP

.

Related Articles